Harder to write compilers for RISC? I would argue that CISC is much harder to design a compiler for.
That being said there’s a lack of standardized vector/streaming instructions in out-of-the-box RISC-V that may hurt performance, but compiler design wise it’s much easier to write a functional compiler than for the nightmare that is x86.
The Vector extension has been ratified since 2021 it’s a standard part of the spec just don’t expect a random microcontroller to support it.
The SpacemiT K1 is 64GCVB and RVA22, doesn’t say which specific RVA22 there’s some without Vector support but it says in “GCVB” so w/e, also, “VLEN 256/128-bit x2 execution width”, if I’m parsing that correctly means you either get 256-bit vector registers or set the whole thing to 128 and then get (roughly) twice the ops/s.
And yes it’s much easier to emit vector code than to deal with the nightmare that’s SIMD. It’s as if Intel would’ve been sensible ages ago and not introduced SIMD but expanded on repnz stosb to make it useful for things other than memcpy. And no Intel has no excuse: Crays existed when they decided on SIMD.
How good are the RISC-V vector instructions implementations IRL? I’ve never heard of them. My experience with ARM is that even on certain data center chips the performance gains are abyssal (when using highly optimized libraries such as dpdk)
Harder to write compilers for RISC? I would argue that CISC is much harder to design a compiler for.
That being said there’s a lack of standardized vector/streaming instructions in out-of-the-box RISC-V that may hurt performance, but compiler design wise it’s much easier to write a functional compiler than for the nightmare that is x86.
The Vector extension has been ratified since 2021 it’s a standard part of the spec just don’t expect a random microcontroller to support it.
The SpacemiT K1 is 64GCVB and RVA22, doesn’t say which specific RVA22 there’s some without Vector support but it says in “GCVB” so w/e, also, “VLEN 256/128-bit x2 execution width”, if I’m parsing that correctly means you either get 256-bit vector registers or set the whole thing to 128 and then get (roughly) twice the ops/s.
And yes it’s much easier to emit vector code than to deal with the nightmare that’s SIMD. It’s as if Intel would’ve been sensible ages ago and not introduced SIMD but expanded on
repnz stosbto make it useful for things other than memcpy. And no Intel has no excuse: Crays existed when they decided on SIMD.How good are the RISC-V vector instructions implementations IRL? I’ve never heard of them. My experience with ARM is that even on certain data center chips the performance gains are abyssal (when using highly optimized libraries such as dpdk)